Binary Phase Change Memory (PCM) cells store information with chalcogenide material which transitions reversibly between high and low resistivity states. In a PCM cell which is electrically-probed, the PCM material is inserted in an electrical circuit to measure the resistance of the Phase Change Element (PCE.) In a conventional planar PCM cell, the PCE comprises a film deposited parallel to the plane of a substrate and the PCE is connected to an electrical circuit via a conductive upper and lower electrodes.
There are significant advantages to Random Access Memory (RAM) devices composed of a nonvolatile chalcogenide material, e.g. Ge2Sb2Te5, which transitions between a low resistivity crystalline state and a high resistivity amorphous state. The term “chalcogen” refers to the Group VI elements of the periodic table. Chalcogenide materials comprise alloys of at least one of the Group VI elements, e.g. germanium, antimony, and tellurium.
In the past, chalcogenide materials have been used in PCM devices, especially in the rewritable CD and DVD disks. When a PCM device is employed in semiconductor chips, there are many advantages over other types of memory devices in areas such as scalability, high sensing margin, low energy consumption and cycling endurance. In a common design for chalcogenide memory cells, the data is stored in a flat chalcogenide layer deposited near the end of the Complementary Metal Oxide Semiconductor (CMOS) interconnect process making it ideal for embedded applications. A chalcogenide memory element can be programmed and reprogrammed into high/low resistance states. When a chalcogenide material is in the amorphous phase (known as the RESET state) it has high resistance; but when it is in the crystalline phase, it has low resistance (known as the set state). The ratio of currents between the SET state and the RESET state can be greater than 1,000 times, which provides high sensing margins.
FIG. 1 contrasts the I-V characteristic of a chalcogenide material in the polycrystalline state with the characteristic in the amorphous state. On the one hand, the amorphous state remains near zero in the low voltage region A1, but in the same low voltage region the polycrystalline state material increases in current in the low voltage region B1. On the other hand the amorphous state matches the polycrystalline state B2 in the higher voltage region A2. When the voltage applied to the amorphous material exceeds the threshold voltage (Vt), threshold switching occurs and the material turns into a dynamic “ON” state. In the ON state, the carrier concentration is high and the resistance is as low as it is in the crystalline state.
FIG. 2 shows the curves of temperature vs time for an amorphizing RESET pulse and for a crystallizing SET pulse in a chalcogenide memory element. Adequate energy must be driven into the chalcogenide PCE to change its state from RESET to SET in the dynamic ON state (i.e. for a device in the RESET state.) As shown in FIG. 2, to ensure such “SET programming,” the device temperature must be above the crystallization temperature (Tx) and must be retained, i.e. held, thereabove for time interval (t2) which is the minimum time period required to complete the process of SET the device.
On the other hand, as shown in FIG. 2, for a “RESET program” in which a PCE in a PCM cell is changed from a SET to a RESET state, sufficient energy must also be driven into the chalcogenide memory element and the local temperature must be raised above the melting temperature (Tm). A shorter period of time should be spent above the temperature Tm to avoid heating the surrounding materials. It is critical that rapid quenching during a very short time interval (t1) is required after the local heating to return to the RESET state in which the material of the PCE is in its amorphous phase.
Because the rate of Joule heating of the material of a chalcogenide PCE during the RESET and SET cycles is determined largely by current density, reducing the contact area between the chalcogenide material of the PCE and the adjacent electrode is sufficient to reduce the switched volume. During the RESET cycle, for example, it is not necessary to melt the entire volume of the PCE material if the current density, and thus Joule heating rate, and thus material temperature, is high enough to melt the PCE material near one of the electrodes. After enough PCE material has been amorphized to span the breadth of the current path through the cell, the overall resistance of the PCM cell will be high. Similarly, during the SET cycle, the overall PCM cell resistance will fall once a sufficiently broad path of crystalline material is formed. In both cases, adjacent material may be left in the opposite state without significantly affecting the overall cell resistance.
To read a chalcogenide PCM device, a “read” voltage is applied thereto. Thus, one can sense the current difference resulting from the different device resistance. The read voltage must be lower than the threshold voltage (e.g. 1.2V) to avoid changing the state of the PCE material.
Currently, chalcogenide materials are used in reversible optical information storage elements such as CD-RW and DVD-RW disks. Compounds such as germanium-antimony-tellurium, i.e. Ge2Sb2Te5 (GST,) can change phase from an amorphous state to a crystalline state in about 50 ns after proper exposure to a laser beam. However, there is the problem that with thinner films the crystallization speed of a GST material tends to decrease. To avoid reduced crystallization speed, tin (Sn) metal is doped into a Ge—Sb—Te compound forming a Ge—Sb—Sn—Te (GSSnT) alloy, increasing the crystallization speed.
FIG. 12 is a table of examples of various binary, ternary and quarternary PCM alloys suitable for use in PCM cells.
FIG. 3 shows a simplified cell structure of chalcogenide memory device comprising a conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) transfer transistor TT, and a PCE ME. The source region S of the MOSFET transistor TT is connected through a via stud BLS to a metal bit-line wire BL. The drain region D of the MOSFET transistor TT is connected through a via stud DS to the bottom electrode BE of the PCE ME. The gate electrode GE of the transfer transistor TT is connected through a via stud WLS to a metal word-line WL. The PCE ME comprises a sandwich of a top electrode TE, a chalcogenide dielectric material CH and the bottom electrode BE. Both the top and bottom electrodes TE and BE are made of metal or refractory metal, while the dielectric material CH comprises a thin layer of a chalcogenide material. The top electrode TE is connected through a via stud SRS to a Set-Reset Line SRL.
FIG. 4 is a graph of resistance as a function of the number of cycles of operation of a PCM cell for both the SET resistance and RESET resistance which shows the cycling endurance of a chalcogenide PCM cell over many cycles, as reported by Stefan Lai, et al., in “Current Status of the Phase Change Memory and its Future,” Electron Devices Meeting, 2003. IEDM '03 Technical Digest, IEEE International 8-10 Dec. 2003 Page(s):10.1.1-10.1.4. Thus, one can conduct SET/RESET cycles for a lifetime of more than 1E12 times which is much higher than the lifetime of about 1E5 cycles of a conventional flash memory device.
FIGS. 5A and 5B show two alternative prior art PCM cell designs which employ edge contact to reduce switching current and which are described by Lai et al. cited above. As employed in FIGS. 5A and 5B based upon the Lai et al. paper, there is the top metallization M1, and the bottom metallization M0. Several electrodes are provided including a top electrode TE, a top electrode contact TEC, a bottom electrode BE, and a bottom electrode contact BEC. The PCM (Phase Change Material) is composed of GST as indicated in FIGS. 5A and 5B. Cells of this design are quite common in the literature.
To prevent interference by altering the resistance as a result of interaction with neighboring cells in a multi-bit device, adjacent memory cells must be isolated from each other electrically. This is conventionally accomplished by patterning the PCM materials and the electrode films, typically by a subtractive process such as etching or Chemical-Mechanical Polishing (CMP). Initially, the PCM and electrode materials are deposited as continuous films. Then, subsequently portions of those films are removed between adjacent cells to provide separate cells adjacent to each other.
One difficulty with conventional methods for cell delineation is that the PCM materials are typically fragile and easily damaged by chemicals used in the etching or CMP polishing processes and subsequent cleaning steps. We have observed that the sidewalls of the PCM layers are exposed to attack by chemicals which can alter the characteristics thereof.